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Serial Character Format Converter

IP.com Disclosure Number: IPCOM000094657D
Original Publication Date: 1965-Apr-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Meltzer, D: AUTHOR

Abstract

This apparatus utilizes a shift register operated in a controlled manner to enable alteration and rearrangement of serial data. The shifting of the register is interrupted from time to time. This occurs when a bit is transmitted directly from the input to the output so as to assume a This apparatus utilizes a shift register operated in a controlled manner to enable alteration and rearrangement of serial data. The shifting of the register is interrupted from time to time. This occurs when a bit is transmitted directly from the input to the output so as to assume a new position in the pulse train. It also occurs at other times when a locally generated sync bit is to be inserted in the output train. The time for sync bit insertion is provided either by a gap in the incoming pulse train or by a bit which is to be deleted.

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Serial Character Format Converter

This apparatus utilizes a shift register operated in a controlled manner to enable alteration and rearrangement of serial data. The shifting of the register is interrupted from time to time.

This occurs when a bit is transmitted directly from the input to the output so as to assume a This apparatus utilizes a shift register operated in a controlled manner to enable alteration and rearrangement of serial data. The shifting of the register is interrupted from time to time. This occurs when a bit is transmitted directly from the input to the output so as to assume a new position in the pulse train. It also occurs at other times when a locally generated sync bit is to be inserted in the output train. The time for sync bit insertion is provided either by a gap in the incoming pulse train or by a bit which is to be deleted.

Serial input data can have a binary code with the bits in the sequential order TBA842lC. T is a special flag bit and C is a parity bit. The desired serial output can have the order S(1)CBAS(2)842l, where S(1) and S(2) are sync bits which are always logical ones, and C is the C bit of the input. Shift register 10 is operated in a programmed manner by time pulse distributor 12. This also times the operation of gates 14 and 16 and delivers the S(1) and S(2) pulses on lines 18 and 20.

At time 1, Gate 16 is operated to block pulse T of the input, and then, at times
2...7, to admit bits B, A, 8, 4, 2 and 1 to register 10...