Browse Prior Art Database

Device Tailoring Procedure

IP.com Disclosure Number: IPCOM000094686D
Original Publication Date: 1965-Apr-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Smith, MG: AUTHOR

Abstract

A method is disclosed for tailoring the transconductance g(m) of insulated gate field-effect transistors. Elongated source and drain electrodes 1 and 3 are formed in semiconductor wafer 5. Gate electrode metallization is deposited over a thin insulating film, not shown, and between source and drain electrodes 1 and 3 as a primary section 7 and a number of secondary sections 9, 11...N.

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Device Tailoring Procedure

A method is disclosed for tailoring the transconductance g(m) of insulated gate field-effect transistors. Elongated source and drain electrodes 1 and 3 are formed in semiconductor wafer 5. Gate electrode metallization is deposited over a thin insulating film, not shown, and between source and drain electrodes 1 and 3 as a primary section 7 and a number of secondary sections 9, 11...N.

Since transconductance g(m) is directly proportional to the width of the gate electrode, transconductance g(m) is tailored by connecting section 7 and one or more of sections 9, 11...N during the normal device interconnection metallization. Unconnected secondary sections. 9, 11...N are connected to an appropriate potential, e.g., grounded. This occurs during interconnection metallization to insure that they do not attain a potential by floating which could cause conduction between source and drain electrodes 1 and 3.

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