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Planar Scanistor Arrays

IP.com Disclosure Number: IPCOM000094687D
Original Publication Date: 1965-Apr-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Stern, E: AUTHOR

Abstract

This fabrication procedure results in either one-dimensional or two-dimensional scanistor arrays. These are planar in structure. With regard to the arrays, the light is incident upon the diode junctions themselves with minimum losses due to intervening media.

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Planar Scanistor Arrays

This fabrication procedure results in either one-dimensional or two- dimensional scanistor arrays. These are planar in structure. With regard to the arrays, the light is incident upon the diode junctions themselves with minimum losses due to intervening media.

A silicon wafer has a pattern of bars formed on one surface. This can be accomplished in a number of ways. Photoetching techniques can be employed. An aluminum mask with the desired pattern can be placed or evaporated onto the silicon surface and reverse sputtering used to form channels in the wafer. A layer of silicon dioxide is formed on the etched side of the wafer by reactive sputtering. This film need not be more than 1 micron thick. The thickness of the structure is then built up further by sputtering, for example, by crystalline silicon.

The top of the original wafer is removed by etching, lapping, or reverse sputtering until the oxide surface is revealed. An additional oxide is now applied to serve as a diffusion mask. A hole pattern is etched in the silicon dioxide, followed by a diffusion to form diode functions. An aluminum metallization is now made over the entire surface. It can be heat-cycled to alloy aluminum in contact with the silicon. Selective etching is used to remove all the aluminum except the narrow interconnections between corresponding diodes of the respective bars. Suitable ohmic contact is made to the two bars. The surface can be further protected by reacti...