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Fabrication of Planar Arrays of Semiconductor Chips by Epitaxial Growth

IP.com Disclosure Number: IPCOM000094689D
Original Publication Date: 1965-Apr-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Yu, HN: AUTHOR

Abstract

For planar arrays, semiconductor lands with minimal electrical coupling between one another are formed by epitaxial or selective epitaxial growth. A single crystal semiconductor substrate such as Ge or Si with suitable surface treatment is used as a starting material. Through ultrasonic cutting, photoresist etching or selective reverse sputtering, a prescribed mosaic pattern of mesa structures is produced on the substrate. A layer of insulator, such as silicon dioxide is formed on the surface by any of the several methods such as thermal oxidation, reactive sputtering, r-f sputtering, pyrolytic decomposition, etc.

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Fabrication of Planar Arrays of Semiconductor Chips by Epitaxial Growth

For planar arrays, semiconductor lands with minimal electrical coupling between one another are formed by epitaxial or selective epitaxial growth. A single crystal semiconductor substrate such as Ge or Si with suitable surface treatment is used as a starting material. Through ultrasonic cutting, photoresist etching or selective reverse sputtering, a prescribed mosaic pattern of mesa structures is produced on the substrate. A layer of insulator, such as silicon dioxide is formed on the surface by any of the several methods such as thermal oxidation, reactive sputtering, r-f sputtering, pyrolytic decomposition, etc.

By using photoetching, small holes are etched through the insulator or the oxide at desired locations in the valleys. Selective epitaxial growth is used to grow semiconducting material through etched holes on the oxide and to fill the valleys. After lapping and polishing procedures, the wafer is now ready to be used for device fabrication. These chips are isolated electrically from one another by the insulating layer. At the place where the epitaxial growth takes place, a PN junction is used to provide isolation, for instance, if the original substrate is P- type, the epitaxial material is N-type. A minimal of electrical coupling is therefore provided among chips.

In an alternative method using photoetching, a relatively large patch of the insulator or oxide in the valley is removed...