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Field Effect Transistor Read Only Storage Unit

IP.com Disclosure Number: IPCOM000094691D
Original Publication Date: 1965-Apr-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Gurski, CS: AUTHOR

Abstract

Field effect transistors (FET's) are arranged i a matrix array of rows and columns. Lies Vs connect the source of each FET to a voltage source. The outputs or drains of each FET in a particular row are connected in parallel to a respective row line R. The gates of all FET's in a particular column are connected in parallel to a respective word lie G via leads 1, if a 1 bit is to be stored. Otherwise, leads 1 are either etched away or initially never deposited.

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Field Effect Transistor Read Only Storage Unit

Field effect transistors (FET's) are arranged i a matrix array of rows and columns. Lies Vs connect the source of each FET to a voltage source. The outputs or drains of each FET in a particular row are connected in parallel to a respective row line R. The gates of all FET's in a particular column are connected in parallel to a respective word lie G via leads 1, if a 1 bit is to be stored.

Otherwise, leads 1 are either etched away or initially never deposited.

To provide amplification and eliminate the need for high-gain sense amplifiers, each row line R terminates at the gate of an FET 2, having its source connected to V(s) and drain connected to an output line O. An FET 3 has its gate and drain connected to drain voltage line V(d) and its source connected to a respective output line O. An FET 4 has its gate and drain connected to V(d) and its source connected to a respective R. FET's 3 ad 4 serve as active loads to the respective row line R ad output line O. Diffusion to metallization connections occur at points 5.

If G(1) is driven, a 1 and 0 are sensed in O(1) and O(2), respectively, amplified by the respective FET's 2 ad 3.

To fabricate this unit, assuming N-channel FET's are to be used, polished P- type silicon wafer substrates are masked for respective sources and drains. The N-type diffusions are vacuum deposited, followed by masking for the metallization to diffusion connections at 5. After growth of the SiO(...