Browse Prior Art Database

Terminal Polling from a Delay Line Buffer

IP.com Disclosure Number: IPCOM000094703D
Original Publication Date: 1965-May-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Smith, RH: AUTHOR

Abstract

The top drawing shows a central processor controlling a plurality of remote stations designated station one, station two, etc. The system permits the processor controller to transmit data to and receive data from the stations.

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Terminal Polling from a Delay Line Buffer

The top drawing shows a central processor controlling a plurality of remote stations designated station one, station two, etc. The system permits the processor controller to transmit data to and receive data from the stations.

In one of the operations commonly performed in systems, the central processor sequentially sends addresses via the transmission line to determine if any of the stations desire to transmit information to the processor. This is termed polling. In order to facilitate the sequential transmission of addresses to the various stations connected to the output line, these addresses are stored in circulating delay line 10. As the addresses are emitted from delay 10, logic 11 transmits them on the output line.

Logic 11 also sets a tag which can merely consist of one bit following the addressing which indicates that the particular address has been transmitted. If, after an address is sent on the output line, one of the stations desires to transmit information to the controller processor it sends a signal on the transmission line to logic 11. Logic 11 then ceases to send addresses out on the transmission line. The data which it receives from the transmission line is stored in the places provided in the delay line between addresses. The format of the data and addresses in the delay line is shown in the lower drawing. When a station stops sending data to the central processor, the logic again begins sending addres...