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Detection Circuit for Record Cell Identifier

IP.com Disclosure Number: IPCOM000094705D
Original Publication Date: 1965-May-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 31K

Publishing Venue

IBM

Related People

Sorg, JH: AUTHOR [+3]

Abstract

Distinguishing a record cell identifier from the normal data is accomplished if an all 1's identifier pattern is recorded at a nominal frequency lower than the frequency of the normal data. This circuit, along with a binary counter, digitally detects a predetermined number of bits to indicate the presence of the identifier. Each detected bit is delayed and then employed to establish a time detection window for the next bit of the identifier.

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Detection Circuit for Record Cell Identifier

Distinguishing a record cell identifier from the normal data is accomplished if an all 1's identifier pattern is recorded at a nominal frequency lower than the frequency of the normal data. This circuit, along with a binary counter, digitally detects a predetermined number of bits to indicate the presence of the identifier. Each detected bit is delayed and then employed to establish a time detection window for the next bit of the identifier.

The circuit employs a plurality of set-reset latches 1...5 arranged in a substantially sequential manner with appropriate And's 11...14 and a tapped delay device. In this particular arrangement, the normal data is recorded at 2.50 megacycles, thus, recurring every 400 n sec. The record cell identifier is recorded at 1.667 megacycles and has a period of 600 n sec.

During a search for the record cell identifier, latch 1 is placed in the on operating mode. Latch 2 is a leading edge detector circuit. The reset for latch 2 is removed with the on condition of latch 1. It is enabled by the complement of a data bit and provides a signal to And 11. This also responds to the data pulse and to the indication of the search mode from latch 1. On the concurrence of all of these pulses, an indication is provided to the tapped delay device. This indication is the rise of the first data bit following the enabling of latch 1.

Latch 3 establishes the time detection window. For detection of the next identifier bit, the rise of the bit must occur during the window. As shown in the timing diagram, the delay device provides the set pulse for latch 3, 500 n sec. after And 11 responds to the occurrence of the original identifier pulse. Latc...