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Clock Pulse Circuit

IP.com Disclosure Number: IPCOM000094707D
Original Publication Date: 1965-May-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Genko, AN: AUTHOR

Abstract

This circuit for generating a series of clock pulses comprises a delay line 10. The output, top waveform, of the opposite states of trigger 12 is coupled to opposite ends of delay 10. Two taps 14 and 16 are provided on delay 10. The step function signals coupled to delay 10 are absorbed in matching resistors 18 at the other end of delay 10.

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Clock Pulse Circuit

This circuit for generating a series of clock pulses comprises a delay line 10. The output, top waveform, of the opposite states of trigger 12 is coupled to opposite ends of delay 10. Two taps 14 and 16 are provided on delay 10. The step function signals coupled to delay 10 are absorbed in matching resistors 18 at the other end of delay 10.

Level sense amplifiers 20 and 22 are responsive to a positive voltage shift. The sensing level of amplifiers 20 and 22 is controlled by voltage VR which is developed by resistor 24. The signals thus generated are useful for timing applications in which two related timing signals are required. An example of this requirement is a memory operation in which both a Long Read and a Long Write timing signal and also Short Read and Short Write timing signals are required. The output from the ends of delay 10 is coupled to condition And 26 when the Read signal is present to produce at terminal 28 the second waveform. The fourth waveform is produced at terminal 32 when And 30 is conditioned by the presence of the Write signal.

The signal sensed at the delay 10 taps is coupled to set latch 34. The output of latch 34 is coupled to condition And 36 or 40 by the Read or Write signal to generate either the third or fifth waveform. Latch 34 is reset by end of pulse sensed by LSA 20.

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