Browse Prior Art Database

Data Transmission Synchronizing System

IP.com Disclosure Number: IPCOM000094725D
Original Publication Date: 1965-May-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Isberg, C: AUTHOR [+2]

Abstract

This method provides bit phase reversals, for clock synchronizing purposes, in a stream of serial bits during idle periods when normal data bit reversals are not occurring. The method is particularly applicable to systems which transmit data in serial form. The systems use a clock in the data receiver which extracts clocking information contained in the bit reversals or transition points to synchronize a bit sample clock.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 79% of the total text.

Page 1 of 2

Data Transmission Synchronizing System

This method provides bit phase reversals, for clock synchronizing purposes, in a stream of serial bits during idle periods when normal data bit reversals are not occurring. The method is particularly applicable to systems which transmit data in serial form. The systems use a clock in the data receiver which extracts clocking information contained in the bit reversals or transition points to synchronize a bit sample clock.

In the system, data from several independent sources is multiplexed or merged into a single stream of serial bits. Each bit occupies its own unique time slot. The data receiver uses a clocking system which requires a certain percentage of reversals in the stream of serial bits. This is in order to provide information to a bit sample clock which synchronizes to the data. Each data source is assigned a numbered time slot in the serial bit stream. The logical sense, 1 or 0, of all even numbered bits is inverted before they are merged into the single serial bit stream.

This technique has the property of generating phase reversals in the serial bit stream during periods when the data-sources are quiescent or inactive. By definition, the quiescent state of all data sources must be the same logical sense, either 1 or 0. At the data receiver the logical sense of all even numbered lines is re-inverted after sampling to restore the data to its original reference. Independence of the data sources during active periods...