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Multi Input Latch

IP.com Disclosure Number: IPCOM000094789D
Original Publication Date: 1965-Jun-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Goldschmidt, RE: AUTHOR [+2]

Abstract

This latch produces up to twelve full-cycle length output signals from twelve selectively energized input signal lines. The input lines are selected sequentially by select signals. To relax the time tolerances on the select signal lines, the inputs and select signals are divided into two groups of alternately gated latches. A data signal line 1, the corresponding select signal line 2, and one of two common gate lines 3 are the three inputs to each of twelve OI's (Nor's) 4. Each OI 4 has the characteristic that all inputs 1, 2 and 3 of an OI 4 must be at a negative signal level before the output line 5 of the Nor will change to a positive signal level.

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Multi Input Latch

This latch produces up to twelve full-cycle length output signals from twelve selectively energized input signal lines. The input lines are selected sequentially by select signals. To relax the time tolerances on the select signal lines, the inputs and select signals are divided into two groups of alternately gated latches. A data signal line 1, the corresponding select signal line 2, and one of two common gate lines 3 are the three inputs to each of twelve OI's (Nor's) 4. Each OI 4 has the characteristic that all inputs 1, 2 and 3 of an OI 4 must be at a negative signal level before the output line 5 of the Nor will change to a positive signal level.

The outputs 5 of the Nor's 4 for the odd-numbered data signals are Dot Ored together into one or more lines which are the inputs to a Nor 6 which also has as an input the line 7 for the A Gate line. Thus, whenever line 7 goes to a positive signal level, the output of Nor 6 goes negative and enables the Nor 4 for the one of the odd number data lines 1 which has a negative data representing signal on its line 1 and a negative select signal on its line 2, to make positive its output line
5. This positive signal on line 5 then holds the Nor's 4 and 6 in the set state so long as the data signal on line 1 and the select signal on line 2 remain negative, which should be for at least the period that the A signal is present on line 7.

As it is desired to maintain, for a complete clock cycle, the positive output signal on lines 5 indicating that the latches of Nor's 4 and 6 have been set, i. e., until gate B on a line 8 is present, a second pair of Nor's 9 and 10 is provided. Nor 9 has its output connected to one of the Dot Or lines 5 and all of these lines 5 are inputs to Nor 10. The output line 11 of Nor 10 is an input of Nor 9 which also has as an input the output line 12 of an Or block 13, driven by both gate lines 7 and 8. When any Nor 4 is set, one line 5 becomes positive and the output 11 of Nor 10 is driven negative. Line 12 is negative so long as neith...