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Block Command Latch

IP.com Disclosure Number: IPCOM000094806D
Original Publication Date: 1965-Jun-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Adler, JG: AUTHOR

Abstract

The communication of the central processing unit (CPU) of a data processing system with input/output devices (I/O) is complicated. This is because input/output devices of various speeds can be attached to the same CPU. A first example is in a system having a very fast input/output device which might receive a signal from a CPU telling it that data is going to be sent to the I/O device. The I/O device can be ready at that moment to receive the data. Therefore, it sends a strobe signal or data request back to the CPU. However, the nature of the instruction can be known before the entire instruction is read out in a serial machine and, therefore, before an entire set of addresses for the write instruction has been determined.

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Block Command Latch

The communication of the central processing unit (CPU) of a data processing system with input/output devices (I/O) is complicated. This is because input/output devices of various speeds can be attached to the same CPU. A first example is in a system having a very fast input/output device which might receive a signal from a CPU telling it that data is going to be sent to the I/O device. The I/O device can be ready at that moment to receive the data. Therefore, it sends a strobe signal or data request back to the CPU. However, the nature of the instruction can be known before the entire instruction is read out in a serial machine and, therefore, before an entire set of addresses for the write instruction has been determined. For this reason, it is possible that the register which holds data to be sent to an I/O device is not yet filled at the time that the strobe or data request is received at the CPU.

A different complication is illustrated by a tape drive which has a mechanical speed limitation. The tape drive might be started as soon as the instruction is known to be a write instruction for that tape drive. It could build up speed during the time that the remaining portions of the instruction would be read and data would be provided to the I/O buffer register. However, in the event that a termination character is sensed in the data itself once this data is available in the buffer, then the tape drive would have been started and would have bui...