Browse Prior Art Database

Nonoverlapping Timing Pulse Generator

IP.com Disclosure Number: IPCOM000094814D
Original Publication Date: 1965-Jun-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Dieffenderfer, JW: AUTHOR

Abstract

This clock pulse generator produces nonoverlapping pulses from a single input pulse train. An n-phase generator consists of two n-stable state circuits interconnected so that a state change in one circuit enables a state change in the other. The pulse train Q is used to clock the state changes.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 85% of the total text.

Page 1 of 2

Nonoverlapping Timing Pulse Generator

This clock pulse generator produces nonoverlapping pulses from a single input pulse train. An n-phase generator consists of two n-stable state circuits interconnected so that a state change in one circuit enables a state change in the other. The pulse train Q is used to clock the state changes.

A three-phase generator employing two tristable circuits is shown. The first tristable circuit has three cascaded stage sections, one for each state. These provide outputs at M1, M2, and M3. Each stage section consists of an And, an Or and an Inverter. The stage sections are interconnected so the output of each is supplied as an input to the Or of all other stages so that only one output can assume an up level at a time. For example, in the initial condition shown in the pulse diagram, M1 is up and both M2 and M3 are down.

The second tristable circuit also includes three stage sections, the outputs of which appear at N1, N2, and N3. Each stage section of this circuit is constructed of two And's and an Inverter.

The output of each Inverter is supplied to one of the And's of each other stage so that only one output assumes a down level at any time. The initial condition shown is N1 up, N2 up, and N3 down.

With the two tristable circuits connected as shown, the first tristable circuit can change state only during an up level of Q. The second circuit can change only during a down level of 0. The new state assumed by each is dependent upon...