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Reflex Delay Line Memory Clock

IP.com Disclosure Number: IPCOM000094815D
Original Publication Date: 1965-Jun-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Dohermann, JE: AUTHOR

Abstract

The delay line clock utilizes the delay line twice for one complete cycle of operation. The line is normally negative and receives a positive shift which travels the length of the line. A plurality of receivers at selected taps on the line respond to the shift to produce, in conjunction with logical circuits, timed pulses. The positive shift received at the last receiver is fed back to reset the latch which causes a negative shift to travel the length of the line. During the transit of this shift, receivers at selected taps on the line, respond to the shift to produce additional timed pulses. When used as a memory clock, the time period during which the positive shift travels the line length is utilized to control the read portion of the memory cycle.

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Reflex Delay Line Memory Clock

The delay line clock utilizes the delay line twice for one complete cycle of operation. The line is normally negative and receives a positive shift which travels the length of the line. A plurality of receivers at selected taps on the line respond to the shift to produce, in conjunction with logical circuits, timed pulses. The positive shift received at the last receiver is fed back to reset the latch which causes a negative shift to travel the length of the line. During the transit of this shift, receivers at selected taps on the line, respond to the shift to produce additional timed pulses. When used as a memory clock, the time period during which the positive shift travels the line length is utilized to control the read portion of the memory cycle. The time period during which the negative shift travels the line length is utilized to control the write portion of the cycle.

The circuit can be operated as a free running clock by utilizing the dotted connection shown at B. A typical receiver configuration is shown within the dashed box labeled RCVR.

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