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Recomplementing High Order to Low Order

IP.com Disclosure Number: IPCOM000094822D
Original Publication Date: 1965-Jun-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Gurski, CS: AUTHOR [+2]

Abstract

When operating a serial-by-bit binary adder in the difference mode, the difference formed by the subtraction can be in the 10's complement form and recomplementation is necessary. By using a right-hand zero (RHZ) latch as one control, and a Carry Flag (CF) as another, it is possible to recomplement from high-order to low-order. The time is saved which would be required by the extra cycle in recomplementing from low-order to high-order, since the arithmetic operation is performed from low-order to high-order.

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Recomplementing High Order to Low Order

When operating a serial-by-bit binary adder in the difference mode, the difference formed by the subtraction can be in the 10's complement form and recomplementation is necessary. By using a right-hand zero (RHZ) latch as one control, and a Carry Flag (CF) as another, it is possible to recomplement from high-order to low-order. The time is saved which would be required by the extra cycle in recomplementing from low-order to high-order, since the arithmetic operation is performed from low-order to high-order.

In the subtract operation, the RHZ latch is set at the start of a word. If a zero digit comes off the delay line, along with the presence of the RHZ, a Digit Flag (DF) is set to that digit position. The first non-zero digit resets the RHZ. Thus, the DF acts as a memory device to signify the end of high-order to low-order recomplementation.

Whenever a borrow is effected, the next higher order digit is tagged by a CF. The presence of CF in a digit position signifies that an extra 1 must be subtracted from the 10's complement of the digit, resulting in a correct complementation.

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