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Preparing Silicon with Electrically Isolated Regions

IP.com Disclosure Number: IPCOM000094881D
Original Publication Date: 1965-Jun-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Tansal, S: AUTHOR

Abstract

This technique is for isolating device areas in a planar wafer structure.

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Preparing Silicon with Electrically Isolated Regions

This technique is for isolating device areas in a planar wafer structure.

One end portion of silicon rod I of A is etched in checkerboard fashion, for example, by spark-cutting, ultrasonic cutting, etc. Such etching defines a desired number of spaced columns 3, each corresponding to a device area in the final wafer structure of C. Rod 1 is then oxidized to form oxide layer 5. Voids between columns 3 are filled with suitable material 7, e. g., grown polycrystalline silicon, as shown in B. Such material has sufficient adhesion with oxide layer 5 to support the final wafer structure and is capable of withstanding high temperatures, e.g., in excess of 1200 degrees C, attained in the fabrication process.

Silicon rod 1 is then sliced into wafers as indicated by the dashed lines in B to obtain the planar wafer structures shown in C. The final wafer structure is defined by device areas 3. Each area is surrounded by a thin layer of silicon dioxide 5 and supported in fixed-spatial relationship in the polycrystalline silicon material 7.

The planar wafer structure of C can be subsequently trimmed to provide congruent device areas.

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