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Fabrication Technique for Integrated Circuit Packaging

IP.com Disclosure Number: IPCOM000094882D
Original Publication Date: 1965-Jun-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Stern, E: AUTHOR [+2]

Abstract

This technique is for defining thin film dielectric patterns by the use of a DC reverse sputtering process.

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Fabrication Technique for Integrated Circuit Packaging

This technique is for defining thin film dielectric patterns by the use of a DC reverse sputtering process.

Semiconductor wafer 1, e.g., silicon, having a thin oxide coating 3 is positioned on cathode 5 positioned within shield 7. Pattern-defining mask 9 formed of conductive material, e.g., aluminum, is positioned in contact over the surface of coating 3 and maintained at cathode potential by conductor strips 1 1. When DC voltage is applied between cathode 5 and anode 13, a glow discharge occurs in the argon atmosphere containing sufficient oxygen to slightly oxidize mask 9. The aluminum oxide greatly retards sputtering of the mask material. Oxide coating 3 and mask 9 are concurrently bombarded by ions in the glow discharge, the former being sputtered at a much higher rate. Space charge normally built up in oxide coating 3 is bled-off by mask 9 so that the sputtering process is not inhibited. Previously, DC reverse sputtering processes of thin dielectric films were seriously limited by the space charge induced in oxide coating 3.

In an alternate technique, mask 9 is formed in a predetermined thickness and of selected material having a known sputtering rate compared to that of oxide coating 3. The mask material is removed during the sputtering process. Complete removal of mask 9 indicates the degree of sputtering of exposed surfaces of oxide coating 3.

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