Browse Prior Art Database

Shift Cell for Current Switching Circuits

IP.com Disclosure Number: IPCOM000094885D
Original Publication Date: 1965-Jun-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Schmookler, MS: AUTHOR

Abstract

This shift cell receives binary data at an input A1 or A2 and a set signal at other inputs and advances and holds the data at an intermediate point and at an output x in response to set signals. As the waveform drawing shows, transitions at the output x occur only with a fall in the set signal. The circuit has four current switching circuits designated W, X, Y and Z. A current switch is a group of transistors. There is produced an Or-Invert function at a common connection of collector terminals of some transistors. There is also produced an Or function at the collector terminal of another transistor in the group.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 57% of the total text.

Page 1 of 2

Shift Cell for Current Switching Circuits

This shift cell receives binary data at an input A1 or A2 and a set signal at other inputs and advances and holds the data at an intermediate point and at an output x in response to set signals. As the waveform drawing shows, transitions at the output x occur only with a fall in the set signal. The circuit has four current switching circuits designated W, X, Y and Z. A current switch is a group of transistors. There is produced an Or-Invert function at a common connection of collector terminals of some transistors. There is also produced an Or function at the collector terminal of another transistor in the group.

Current switching groups Y and X each have an emitter-follower connected transistor. This feeds back the Or output to one of the inputs to form a latch. Group Z receives a set signal and the Or-Invert output of group Y. At its Or output, it provides clock information for the latch of group X. At its Or-Invert output, it provides an input to group W. Group W receives the signal at a selected input A1 or A2 and the Or-Invert signal of group Z. Its Or output is connected to the reset input of the group Y latch to provide data information that is appropriately modified by the input from group Z to prevent races.

The Or-Invert output of the group Y latch is connected to an input to the group X latch. In response to clock signals the circuit advances signals at inputs Al or A2 to latch Y and then to latch X.

The circui...