Browse Prior Art Database

Making Isolated Structures

IP.com Disclosure Number: IPCOM000094890D
Original Publication Date: 1965-Jun-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Fowler, AB: AUTHOR [+2]

Abstract

Device areas defined in a silicon wafer are isolated while maintaining interconnections between them.

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Making Isolated Structures

Device areas defined in a silicon wafer are isolated while maintaining interconnections between them.

An N-type epitaxial layer 1 is grown over a P-type semiconductor wafer 3. Device areas 5 are defined by P+-type isolation diffusions 7. Subsequent to device diffusions, not shown, in device areas 5 and metallization of interconnections 9, a dielectric supporting layer 11 is formed, e.g., by sputtering, pyrolytic deposition, etc.

The resulting structure is then preferentially etched by an electrolytic process to remove P-type wafer 3 and P+-type isolation diffusions 7. The structure A is immersed in an electrolytic bath, e.g., hydrofluoric acid, and the P-type wafer 3 is connected at anode potential. The P-type wafer 3 and P+-type isolation diffusions 7 are preferentially etched leaving N-type device areas 5 exposed with interconnections 9 intact and supported on support layer 11.

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