Browse Prior Art Database

Producing Isolated Structures

IP.com Disclosure Number: IPCOM000094896D
Original Publication Date: 1965-Jun-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Caswell, HL: AUTHOR [+2]

Abstract

Registering processes are effected on opposite faces of semiconductor wafer 1. The processes to be registered are device diffusing and chemical etching to electrically isolate the device diffusions.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 76% of the total text.

Page 1 of 2

Producing Isolated Structures

Registering processes are effected on opposite faces of semiconductor wafer 1. The processes to be registered are device diffusing and chemical etching to electrically isolate the device diffusions.

As shown in A, transistors 3 and interconnecting line 5 over genetically- formed insulating layer 7 are initially formed on an N-type epitaxial layer 1A which has been grown on N/+/-type silicon wafer 1B) At least two deep holes 9 are chemically etched along the edge of wafer 1 by conventional photoresist techniques and extend at least to the surface of wafer 1B. Holes 9 correspond to an alignment pattern for registering the chemical etching process to be effected on the opposite surface of wafer 1. Wafer 1 is then cemented to support 11 by appropriate cement 13 having a distinctive color which fills holes 9. For example, wafer 1 is cemented to support 11 by ECCOBOND 51, manufactured by Emerson and Cuming, Canton, Massachusetts. This product has a distinctive black color.

The silicon wafer 1B is then chemically etched with an appropriate solution, e.g., 1 part hydrofluoric acid and 20 parts nitric acid. Such occurs until the alignment pattern defined by holes 9 appears visible against the lighter silicon background.

As shown in B, etched resistant mask 15, formed by conventional photoresist techniques, is aligned with holes 9. A portion of layer 1A remaining between transistors 3 is removed, as indicated by the dashed lines, with a static...