Buffer Storage Device
Original Publication Date: 1965-Jul-01
Included in the Prior Art Database: 2005-Mar-06
To buffer data transfer between two relatively low-speed, asynchronous data handling devices, there is provision for storing randomly presented data serial-by-word, parallel-by-bit on drum 1. There is also provision for subsequently reading the data off drum 1 at random or fixed times on a first-in, first-out basis. Each recorded word consists of data bits D and a flag bit F.
Buffer Storage Device
To buffer data transfer between two relatively low-speed, asynchronous data handling devices, there is provision for storing randomly presented data serial- by-word, parallel-by-bit on drum 1. There is also provision for subsequently reading the data off drum 1 at random or fixed times on a first-in, first-out basis. Each recorded word consists of data bits D and a flag bit F.
Write-read head 2 in operative relation to the recording surface of 1 has a plurality of write-read gaps 4. Each is associated with a write coil 5 and a read coil 6. In addition, 2 includes a flag bit read gap 7 associated with read coil 9 and a flag bit write-erase gap 8 associated with coil 10. Gap 7 is located in advance of 8 by an amount in excess of one word space on 1.
Holdover single-shots 30 and 31 normally have positive outputs. When an input pulse is received by 30, its output drops. Such is for the time it takes 1 to make slightly more than one revolution. At the end of that time, it times out, i.e., returns positive. If a second input is received before timeout, recycling is initiated and the second input becomes the new point of reference for timeout. Single- shot 31 times out after a period slightly in excess of one word space on drum 1. Single-shots 32 and 33 are conventional. The length of an output pulse from 32 is equal to the time it takes a flag bit to move from 7 to a point just in front of 8. An output from 33 is sustained for the time it takes a flag bit to move from 7 to a point just beyond 8.
In data writing, the data input-control device, e.g., a typewriter, card reader, etc., supplies a write mode signal to terminal 21. This signal partially conditions And's 23 and 35, deconditions And 29 through Inverter 26 and places flag driver 16 in condition to supply a flag bit write signal to coil 10. Since the outputs of both 30 and 31 are at their normal positive level, And's 35 and 36 are partially conditioned. The write mode signal completes the conditioning of 35, causing it to activate 36. This partially conditions And 27 and turns on erase driver 17 and erase head 3, insuring that all previous data is cleared from 1.
As soon as the first word is made available on data input bus 13 by the data input device, an execute pulse is supplied to terminal 22. The width of this pulse must be equal to one drum cycle plus the period of 31. This pulse activates 23, enabling 27 which in turn triggers 31 through Or 28. As soon as the output of 31 drops, 35 is deconditioned, turning off 17. The negative transition at the output of 31 also triggers 30 through Inverter 34. This insures that head 3 remains inactivated for the remainder of the write operation and for the subsequent readout operation....