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Data Separator for Double Frequency with Reduced Timing Tolerance Requirements

IP.com Disclosure Number: IPCOM000094911D
Original Publication Date: 1965-Jul-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Holmes, LG: AUTHOR [+2]

Abstract

This is a data detector circuit for separating the interleaved clock and data pulses in double-frequency recording.

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Data Separator for Double Frequency with Reduced Timing Tolerance Requirements

This is a data detector circuit for separating the interleaved clock and data pulses in double-frequency recording.

This circuit includes three single-shots T1, T2, and T3. The period of T1 is set at 35% of the clock period CP, i.e., the time from the beginning of one clock pulse to the beginning of the next clock pulse. The period of T1 represents the minimum time between a clock pulse and a data pulse due to bit shift. T1 is triggered by each clock pulse in the raw data and produces an output 1 which is sent to the processor as a clock pulse. T2 is triggered by the trailing edge of signal 1 and produces an output 2 which forms a window during each clock period. The duration of 2 is set to cover that portion of a clock period during which a data pulse could occur.

Output 2 conditions gate A2 to pass a possible data pulse. Output 2 also blocks gate A1 so that a data pulse cannot restart T1. The appearance of a data pulse during the window 2 starts T3. The period of T3 is so chosen that if it starts at the latest possible time, i.e., data pulse occurring at end of T2 time, T3 still times out before the next clock pulse. Output 3 of T3 provides a data output 3 and it also blocks gate A1. This latter is done to protect against the case where a data pulse overlaps the time out of T2 which could cause an erroneous start of T1.

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