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Parity Bit Generation for a Shift Operation

IP.com Disclosure Number: IPCOM000094921D
Original Publication Date: 1965-Jul-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Smith, JL: AUTHOR

Abstract

Digital operations can be checked by the use of parity bits where the parity of the result is compared to a parity that is predicted as a function of the operation and the parities of the operands.

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Parity Bit Generation for a Shift Operation

Digital operations can be checked by the use of parity bits where the parity of the result is compared to a parity that is predicted as a function of the operation and the parities of the operands.

Parity bits can be generated for shift operations by forming the sum modulo-2 of the original parity bit, the parity bit of the data that is shifted out, and the parity bit of the data that is shifted in, where the latter two bits are obviously derivable as the shift parameter is known. Alternatively. the stored data can be divided into groups of bits, e.g., eight bits, with a parity bit associated with each group.

When the data is shifted by an amount less than or equal to the group size, e.g., eight, the above procedure is applicable. When the shift exceeds the size of a group, the parity bits that are generated in accordance with the above procedure are themselves shifted in a separate shift register to develop the resultant set of parity bits.

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