Browse Prior Art Database

Supervisory Controls

IP.com Disclosure Number: IPCOM000094927D
Original Publication Date: 1965-Jul-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Hackl, FJ: AUTHOR

Abstract

In a processing unit, there are several relatively independent clock control and mode control signal distribution networks. These provide a versatile repertoire of control functions. The unit includes a central processor unit CPU. This is normally controlled by outputs of a read-only store ROS sequence control matrix. CPU contains a main store MS, certain ring counter controls RC and basic data handling circuits. These include an arithmetic unit, a local scratchpad store, a mover unit (logical byte translating network), several registers, and interface, denoted by I/O in the drawing, to channel devices which asynchronously transfer data between the CPU and input/output devices such as tapes, printers, and the like.

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Supervisory Controls

In a processing unit, there are several relatively independent clock control and mode control signal distribution networks. These provide a versatile repertoire of control functions.

The unit includes a central processor unit CPU. This is normally controlled by outputs of a read-only store ROS sequence control matrix. CPU contains a main store MS, certain ring counter controls RC and basic data handling circuits. These include an arithmetic unit, a local scratchpad store, a mover unit (logical byte translating network), several registers, and interface, denoted by I/O in the drawing, to channel devices which asynchronously transfer data between the CPU and input/output devices such as tapes, printers, and the like.

All actions within the CPU are controlled by clocks C and supervisory controls SC. There are four groups of clock lines identified respectively as CPU, ROS, MS, and Supervisory clocks. The CPU clock group feeds all parts of the CPU other than ROS, RC and MS. The ROS clock is coupled only to ROS. The MS clock is coupled to MS and RC. The Supervisory clock group is coupled only to SC. SC contains three clock status triggers CST. These can be conditioned individually to selectively inhibit any combination of CPU, ROS, and MS clocks. When all three triggers CST are set, all clocks except the Supervisory clock group are blocked and the CPU is effectively in a stopped condition. SC also contains control status or mode triggers. The latter register mutually exclusive ROS mode, MS mode, and RC mode indications.

In normal CPU operation, the ROS mode line and all clocks are effective and the MS and RC mode lines are inactive. Movement of intelligence through CPU in this mode is controlled by ROS and elements which can b...