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Electronic Switching Circuits for Multiplication

IP.com Disclosure Number: IPCOM000094931D
Original Publication Date: 1965-Jul-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 84K

Publishing Venue

IBM

Related People

Isberg, CA: AUTHOR

Abstract

This binary multiplier derives partial products from sequentially less significant bits of the operands. Generally, the product is regarded as a summation of the partial products of each multiplier bit with each multiplicand bit, the bit weights being preserved, and is actually formed by taking appropriate combinations. The usual multiplication, in which the partial product combination is the entire multiplicand by a digit of the multiplier, also fits into this algorithm.

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Electronic Switching Circuits for Multiplication

This binary multiplier derives partial products from sequentially less significant bits of the operands. Generally, the product is regarded as a summation of the partial products of each multiplier bit with each multiplicand bit, the bit weights being preserved, and is actually formed by taking appropriate combinations. The usual multiplication, in which the partial product combination is the entire multiplicand by a digit of the multiplier, also fits into this algorithm.

This multiplier iterates x. y = (x'. 2 + x(1))(y'. 2 + y1)i(x'. y'). 4 + (x'. y1). 2 + (y'. x1). 2 + x1. y1 where x and y are the operands, x1 and y1 are the bits corresponding to the iteration, and x' and y' are the prefix bits of the operands excluding x1 and y1.

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