Browse Prior Art Database

Single 6 Bit Delay Line Locator

IP.com Disclosure Number: IPCOM000094932D
Original Publication Date: 1965-Jul-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Botjer, JL: AUTHOR [+4]

Abstract

In transferring randomly produced display data characters into a recirculating delay line buffer store, it is necessary to locate the last character entry as it leaves the buffer, as a reference for each new character entry into the buffer. In this display system, last entry location is accomplished by making use of existing spacer bit cells between consecutive stored characters to store last entry locator signals.

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Single 6 Bit Delay Line Locator

In transferring randomly produced display data characters into a recirculating delay line buffer store, it is necessary to locate the last character entry as it leaves the buffer, as a reference for each new character entry into the buffer. In this display system, last entry location is accomplished by making use of existing spacer bit cells between consecutive stored characters to store last entry locator signals.

Binary video display signals are supplied in 5-bit groups to delay line buffer store DL from an input device IP. The format of the display to be composed from these signals requires that there be a dark dot area, i.e., 0 bit space, between successive 5-bit groups. This space is used in this system to carry last entry locator signals.

When the line is erased by the controls EC, a locator signal, or 1 bit, is inserted in the bit space preceding the first 5-bit entry space. A character available signal supplied by IP and clock signals supplied by timing controls CC enable the controls EC to selectively apply every sixth bit signal emerging from DL to an inhibit input of recirculating And A. Compensating delay CD is inserted to align the inhibit signal derived from the locator bit with the locator bit entering A so that the latter bit is effectively erased from the line. Simultaneously, the locator inhibit signal is forwarded to LP as a transfer character signal in response to which, after a unit bit delay, IP synchronously...