Browse Prior Art Database

Integrator Timer

IP.com Disclosure Number: IPCOM000094971D
Original Publication Date: 1965-Jul-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Smith, R: AUTHOR

Abstract

The circuit produces an output signal that is delayed for a predetermined time interval with respect to the input signal. Waveform a represents an input signal to terminal 1. Waveform b illustrates the charge and discharge action of capacitor C1. Waveform c is the output signal at terminal 2.

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Integrator Timer

The circuit produces an output signal that is delayed for a predetermined time interval with respect to the input signal. Waveform a represents an input signal to terminal 1. Waveform b illustrates the charge and discharge action of capacitor C1. Waveform c is the output signal at terminal 2.

With the input signal up, transistor T1 is saturated and transistor T2 is off. C1 charges up so that the voltage at terminal 3 equals the voltage available at terminal 4. And-Or-Invert (AOI) 5, including transistor T3, is saturated so that the output signal is down.

When the input signal drops as at 6 T1 is turned off. Current flowing through resistor R1 now goes into the base of T2 and C1. This discharges C1 with the discharge taking place linearly. When the voltage at terminal 3 reaches the threshold of AOI 5, as at 7 in waveform b, the output signal rises as at 8. When the input signal returns to its up condition as at 9, the circuit is reset by recharging C1 through resistor R3. The circuit is then ready for another timing cycle.

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