Browse Prior Art Database

Chip Read Only Memory

IP.com Disclosure Number: IPCOM000094977D
Original Publication Date: 1965-Jul-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Heitzman, ET: AUTHOR

Abstract

This read-only memory has transistors arranged in a matrix. Emitter terminals are connected together in columns to form word select drive lines. Collector terminals are connected together in rows to form data output lines. When one of the select drive lines is energized, signals appear on the output lines in a pattern. The latter is established by the connection of the base terminals to a biasing point. Drawings A is an exploded view and drawing B is a side view of the memory.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 93% of the total text.

Page 1 of 2

Chip Read Only Memory

This read-only memory has transistors arranged in a matrix. Emitter terminals are connected together in columns to form word select drive lines. Collector terminals are connected together in rows to form data output lines. When one of the select drive lines is energized, signals appear on the output lines in a pattern. The latter is established by the connection of the base terminals to a biasing point. Drawings A is an exploded view and drawing B is a side view of the memory.

The transistors are small semiconductor chips 1. Three terminals connect to the base, emitter and collector regions of a chip 1. The chips are mounted on support 2. Row conductors 3 and column conductors 4 are also formed on support 2. Such conductors are connected to the appropriate emitter and collector terminals. Conductors 4 form word select drive lines. Conductors 3 form data output lines.

Insulating support 5 has a connector 6 for each base terminal. Support 5 is positioned to insulate the emitter and collector terminals and the row and column conductors 3 and 4 and to provide extensions of the base terminals at the surface of support 5 that is outermost in the drawing. Conductive sheet 7 is positioned to contact the base terminal extensions 6. Sheet 7 is electrically connected to a suitable potential source for biasing the transistors to turn on when their emitter terminals are energized. Holes 8 are formed in sheet 7 to isolate selected base terminals to produc...