Browse Prior Art Database

Level Restoring for Array with Steering Diodes

IP.com Disclosure Number: IPCOM000094978D
Original Publication Date: 1965-Jul-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Genko, AN: AUTHOR

Abstract

In this magnetic core storage device, fast operation is obtained by limiting the capacitive charge which the gates encounter.

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Level Restoring for Array with Steering Diodes

In this magnetic core storage device, fast operation is obtained by limiting the capacitive charge which the gates encounter.

The normal read-write cycle requires that current pass first in one direction along a selected core winding line in array 10... 10n when gates 12 and 14 are operated and then in the other direction when gates 16 and 18 are operated in conjunction with steering diodes 11. The current pulse is controlled by a constant current source 15. Source 15 must discharge the capacitance of all the unselected lines 10a... 10n thus slowing the rise time of the current in the selected lines.

A level restoring circuit is provided to charge the array in a predetermined manner and then maintain the charge until the next cycle. Each group of array lines 10, 20 and 30, which are coupled together at the non-diode end, are connected through a diode 26 to a level restoring circuit. This comprises low impedance switches 22 and 24. These are turned on between read and write cycles to charge the array. The array is charged to +V by switch 22 after array switches 16 and 18 are operated. The array is charged to -V by switch 24 after array switches 12 and 14 have been operated. This circuit provides fast current rise time for the drive pulses. This is because the unselected lines are precharged before the drive current pulses are applied to the lines.

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