Browse Prior Art Database

Gating Network

IP.com Disclosure Number: IPCOM000094995D
Original Publication Date: 1965-Aug-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Forslund, DC: AUTHOR

Abstract

This circuit controllably gates phase-opposed oscillator signals so that only complete signals appear at the outputs. In-phase oscillator signals are applied to terminals 10 and 12. Out-of-phase oscillator signals are applied to terminals 14 and 16. A gate signal is applied via gate input terminal 18 to the 1 side of gated binary triggers A and B as well as to inverter 20. Triggers A and B require coincident inputs to cause them to be set or reset.

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Gating Network

This circuit controllably gates phase-opposed oscillator signals so that only complete signals appear at the outputs. In-phase oscillator signals are applied to terminals 10 and 12. Out-of-phase oscillator signals are applied to terminals 14 and 16. A gate signal is applied via gate input terminal 18 to the 1 side of gated binary triggers A and B as well as to inverter 20. Triggers A and B require coincident inputs to cause them to be set or reset.

The application of a gating signal to terminal 18 partially conditions the 1 side of A and B. It is assumed that the in-phase oscillator signal traverses positively before the out-of-phase signal. Then the positive transient applied to terminal 10 fully conditions the 1 side of A and causes its 1 side output line 22 to produce an up level. This signal partially conditions gate 24 and And 26. When the out-of- phase oscillator signal applied to terminal 16 next traverses to the up potential, gate 24 is fully conditioned and its output conductor thereafter reflects the variations of the out-of-phase oscillator signal. Due to the fact that the 0 side of B is high at this time, the conditioning of And 26 by the 1 side output of A causes the 1 side of the reset trigger to be set to the high level thus partially conditioning And 28. Since the gate signal is inverted by inverter 20, And 28 is inhibited and produces no output.

When the out-of-phase oscillator signal goes positive and fully conditions gate 24, it also sets the 1 side of B to produce an up output on conductor 30. This output partially conditions gate 32 in preparation for the next positive-going transition of the in-phase oscillator signal applied to terminal 12. At such time, the output from gate 32 follows the in-phase oscillations. In addition, And 34 is partially conditioned. Due to the fact that the 0 side of A is at the down level, no output is produced by And 34 into the 0 side of the reset trigger. For this reason, And 36 remains deconditio...