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Browse Prior Art Database

Selection Using Cascaded Counters

IP.com Disclosure Number: IPCOM000095000D
Original Publication Date: 1965-Aug-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Wexler, SB: AUTHOR

Abstract

In data processing equipment, it is customary to condition the performance of certain operations upon the state of a sequence counter. To distinguish particular states of the counter, a decoding logic circuit or matrix is employed to translate each particular state of the counter into a corresponding signal on a unique output line. In certain instances distinguished below, the hardware used in such decoding logic can be considerably reduced.

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Selection Using Cascaded Counters

In data processing equipment, it is customary to condition the performance of certain operations upon the state of a sequence counter. To distinguish particular states of the counter, a decoding logic circuit or matrix is employed to translate each particular state of the counter into a corresponding signal on a unique output line. In certain instances distinguished below, the hardware used in such decoding logic can be considerably reduced.

An example of a fully parallel decoder coupled to binary counter C having n + 1 cascaded stages is at A. Particular states of C are detected by separate count selecting circuits CS within decoding logic DL. For example, CS3 provides a unique signal output when C is in the state representative of the number 3, i.e.,
00...011. In general, CSx provides a unique output when C is in a state representative of the number x. The logic of each CS requires coincident examination of all stages Cn...Co of C. For example, the output of CS3 is a function of the outputs of the first two stages of C Anded with a Nor function of the remaining n-1 outputs of C. Using certain solid state circuits, for example, SLT logic, the maximum number of input lines permitted to load one Nor circuit is limited. Thus, if n is a large number, the additional Nor circuits required in circuits such as CS3 becomes significant.

In an alternative decoding logic at B, C is restricted to always count unidirectionally from a referenc...