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Browse Prior Art Database

Single Track Error Correction on Multichannel Tapes

IP.com Disclosure Number: IPCOM000095013D
Original Publication Date: 1965-Aug-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Sih, KY: AUTHOR

Abstract

The circuit controls the correction of errors restricted to any single track in a tape data block. Whenever a tape block is read, the respective tape tracks of TR-1...TR-N are applied as parallel inputs to both a cyclic redundancy check circuit CRCC and a longitudinal redundancy check register LRCR. LRCR comprises a plurality of binary triggers. A respective binary trigger sums modulo-2 the 1 bits received from its respective tape track. Such provides an indication of the error status of the track at the end of the block after the corresponding bit of a longitudinal redundancy check character is received. CRCC is a cyclic redundancy check circuit. This can be a recirculating shift register which receives the respective tape track bits in parallel in different positions of the register.

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Single Track Error Correction on Multichannel Tapes

The circuit controls the correction of errors restricted to any single track in a tape data block. Whenever a tape block is read, the respective tape tracks of TR-1...TR-N are applied as parallel inputs to both a cyclic redundancy check circuit CRCC and a longitudinal redundancy check register LRCR. LRCR comprises a plurality of binary triggers. A respective binary trigger sums modulo- 2 the 1 bits received from its respective tape track. Such provides an indication of the error status of the track at the end of the block after the corresponding bit of a longitudinal redundancy check character is received. CRCC is a cyclic redundancy check circuit. This can be a recirculating shift register which receives the respective tape track bits in parallel in different positions of the register. CRCC sums them modulo-2 with the bits stored in or transferred to the respective register positions.

CRCC has end-around feedback and it also can have intermediate feedback. CRCC is shifted one bit position after each set of parallel bits is received from the tracks. A cyclic redundancy check character is provided at the end of each block. Thus, if there is no error in the block, a predetermined no-error pattern is provided after the cyclic redundancy check character is received. An error test circuit ET looks for this predetermined no-error pattern after each block is received. ET indicates an error if such predetermined pattern is not obtained.

Each And 21-1...21-N has an input connected to the output of a different one of the binary triggers of LRCR. Also, all And's have an i...