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Realtime Checking of Selector Channel Sequence Controls by Time Shared Central Processor Sequence Controls

IP.com Disclosure Number: IPCOM000095014D
Original Publication Date: 1965-Aug-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Crocket, PN: AUTHOR [+2]

Abstract

In certain processor systems, a section of the sequence controls of the central processor unit CPU can participate in the control of certain input/output functions. Organizationally, such a section could be part of a common channel system controlling an interface between CPU and several relatively asynchronous channel units.

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Realtime Checking of Selector Channel Sequence Controls by Time Shared Central Processor Sequence Controls

In certain processor systems, a section of the sequence controls of the central processor unit CPU can participate in the control of certain input/output functions. Organizationally, such a section could be part of a common channel system controlling an interface between CPU and several relatively asynchronous channel units.

Certain of the channel units, known as selector channels SC, house a buffer data register DR and internal sequence controls including a position register PR and cycle counter CC. When a channel SC is ready to transfer information between DR and the main store MS of CPU, its internal sequence controls issue a particular request for service on bus K. This initiates a predetermined sequence of control communication between SC and the common channel system. In the absence of a circuit failure, at predetermined phases of this sequence of communications, PR and CC should be in predetermined states.

Interleaved with its real time communication control function, the common channel system, by adaptation, assumes test states in which it is effective to compare the current states of PR and CC to reference information. The latter is stored within the CPU which corresponds to the expected states of PR and CC in a correctly functioning system. A mismatch detected in such a comparison is taken as representative of a circuit or synchronization failure....