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Real Time Log Out of Selector Channel Control Latches

IP.com Disclosure Number: IPCOM000095015D
Original Publication Date: 1965-Aug-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Crockett, PN: AUTHOR [+2]

Abstract

In drawing A, an arrangement is shown for checking the conditions of certain selector channel control latches. Such occurs at predetermined channel sequence control cycles using central processor CPU checking circuits P.

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Real Time Log Out of Selector Channel Control Latches

In drawing A, an arrangement is shown for checking the conditions of certain selector channel control latches. Such occurs at predetermined channel sequence control cycles using central processor CPU checking circuits P.

In this particular CPU, intelligence is handled in 32-bit word units, each accompanied by four parity bits. The word units are subdivided into four byte groups. Each byte contains eight consecutive bits of the word. The bytes ordinarily have predetermined parity relationships to corresponding ones of the parity bits. For example, a word consisting entirely of zero bits, i.e., four all-zero bytes, provides a satisfactory parity indication when checked by parity checking circuits P, if the values of the transmitted parity bits are all ones. The same CPU also contains an all-zeros checking circuit Z for responding in a unique sense to a word consisting exclusively of zero bits.

In checking the conditions of selector channel controls during channel operations, use is made of the CPU checking circuits P and Z. The control information is organized into groups of thirty-six bits. These groups are individually coupled via a thirty-six wire bus to P. Thirty-two of the thirty-six wires of this bus deliver associated signals to Z as an intelligence word unit. The coupling of any signal group to the bus is programmed to occur only when the thirty-two bits transmitted to Z are all zero representations. Als...