Browse Prior Art Database

Parity Checked Data Transfers from Channel to Main Store

IP.com Disclosure Number: IPCOM000095016D
Original Publication Date: 1965-Aug-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 63K

Publishing Venue

IBM

Related People

Crockett, PN: AUTHOR [+2]

Abstract

In transmitting digital data from a channel to read-write main store MS of central processing unit CPU, a parity check on the data is performed as it approaches buffer data register SDR of the store thus verifying that the transmitted data is not altered in transmission. To conserve transmission time, parity check circuit PC is an off-line type. It functions to check the parity. It does not substitute signals representing newly calculated parity digits in place of the transmitted parity signals received with the channel data. The opposite, off-line, type of parity checking circuit, effective to check parity and substitute newly generated parity signals for the originally transmitted parity signals, introduces additional delays into the transmission path.

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Parity Checked Data Transfers from Channel to Main Store

In transmitting digital data from a channel to read-write main store MS of central processing unit CPU, a parity check on the data is performed as it approaches buffer data register SDR of the store thus verifying that the transmitted data is not altered in transmission. To conserve transmission time, parity check circuit PC is an off-line type. It functions to check the parity. It does not substitute signals representing newly calculated parity digits in place of the transmitted parity signals received with the channel data. The opposite, off-line, type of parity checking circuit, effective to check parity and substitute newly generated parity signals for the originally transmitted parity signals, introduces additional delays into the transmission path.

Checking circuits of the in-line type are generally included in extensive networks, such as are in parallel fast-carry binary adders. In these, the information signals invariably pass through a series of logic circuits. The latter have a characteristic delay greater than that of the off-line checking circuit. The advantage of an in-line checking circuit is that it generates and transmits new parity signals. These are correctly matched to the transmitted intelligence, so that as the intelligence circulates from one station to another in a processing system, only a single error indication and one corresponding processing interruption are encountered.

While intelligence passed by an in-line checking circuit may have been altered, and therefore be useless as intelligence, the parity digits emitted by the checking circuits are invariably correctly matched to the intelligence. Thus, should it be necessary to ignore a single error detected during the processing of many intelligence items, use of an in-line checking circuit guarantees that only one error indication is produced, i.e., only when the transmission error is first detected by the checking circuit.

In the CPU shown in drawing 1, the duration of a read-write cycle of MS is four times the duration of an action cycle of CPU. An action cycle of CPU is the time ordinarily required to translate intelligence from one CPU register, such as L or R, through the adder A, adder latches AL, and bus B, to the same or another CPU register, or to data register SDR, or to address register SAR associated with MS. A transfer from the channel buffer register through AL to SDR also requires one CPU action cycle.

If, in a transfer from the channel to SDR, a parity error is detected by PC, the sequence control SC of CPU can be diverted to an interrupt type routine so that the cause of the error can be determined. Alternatively, the sequence controls can be conditioned to ignore the error. Without further action on the part of the sequence controls this results in storage within MS of mismatched parity and intelligence bits received from AL. Upon subsequent retrieval from MS, these same bits pass...