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No Ripple Parallel High Low Equal Comparator

IP.com Disclosure Number: IPCOM000095020D
Original Publication Date: 1965-Aug-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Kennedy, JC: AUTHOR [+2]

Abstract

A high-low-equal comparison of two bytes of binary data is performed in parallel by this circuitry. Significance is given to the higher order bits so that, if a true high or low condition occurs, all the lower order bits of the opposite condition are inhibited.

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No Ripple Parallel High Low Equal Comparator

A high-low-equal comparison of two bytes of binary data is performed in parallel by this circuitry. Significance is given to the higher order bits so that, if a true high or low condition occurs, all the lower order bits of the opposite condition are inhibited.

The circuitry is formed of high and low banks of And's, A1, A3, A5 ... and A2, A4, A6 ..., respectively. Each order of the binary numbers is compared by a pair of these And's. Thus, A1 compares the bit X0 and the complement of the bit Y0 to indicate if X0 is greater than Y0. Similarly, A2 compares Y0 and the complement of the bit X0 to determine if X0 is less than Y0. The corresponding bits of the binary numbers are compared in the lower order And's. Each lower order And accepts as an inhibiting input the outputs from all higher order And's of the opposite bank. Thus, if A1 provides an output indicating that X0 is greater than Y0, And's A4 and A6 are inhibited without the necessity of a rippling effect taking place through each order of comparison.

All indications of high comparison from A1, A3 and A5 are Ored at Or 1. All low indications from A2, A4 and A6 are Ored at Or 2. Sampling of the outputs from Or's 1 and 2 occurs at A7 and A8, respectively, for setting high latch L1 and low latch L2. When set, one latch indicates at its output the result of the comparison of the two bytes of binary data. If neither latch is set, then an indication of an equal condition...