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Associative Memory Using Analog Summing Technique

IP.com Disclosure Number: IPCOM000095045D
Original Publication Date: 1965-Aug-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Beisner, HM: AUTHOR

Abstract

An associative memory utilizing an analog output summing technique performs a digit-by-digit comparison of an input word with a plurality of different response words stored in the associative memory. Associative memory 10 comprising core arrays 12 and 14 is used to store certain response words in the individual columns of cores. For instance, cores Cl1..C100, store a first response word. Cores C1...C100 store the complement of that response word. These response words are to be compared subsequently to a number of different input words. The input words are presented to driver circuits B1...B100. The complements of the input words are presented to driver circuits B1...B100. Threading the individual cores of arrays 12 and 14 is a plurality of sense lines S1...S100. Each sense line terminates in a threshold device L1...L1004.

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Associative Memory Using Analog Summing Technique

An associative memory utilizing an analog output summing technique performs a digit-by-digit comparison of an input word with a plurality of different response words stored in the associative memory. Associative memory 10 comprising core arrays 12 and 14 is used to store certain response words in the individual columns of cores. For instance, cores Cl1..C100, store a first response word. Cores C1...C100 store the complement of that response word. These response words are to be compared subsequently to a number of different input words. The input words are presented to driver circuits B1...B100. The complements of the input words are presented to driver circuits B1...B100. Threading the individual cores of arrays 12 and 14 is a plurality of sense lines S1...S100. Each sense line terminates in a threshold device L1...L1004. Interposed between the individual sense lines and their associated threshold devices are individual diodes D1...D100. Biasing each threshold device off is a source of bias voltage 32. This voltage must be exceeded before the individual threshold devices are activated.

In operation, an input word is entered to registers B1...B100. The complement of that input word is stored in registers B1...B100. The word and its complement are then successively compared with the individual response words and their complements, stored in arrays 12 and 14. For every similarity between digits of the input word and...