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Parallel Transistor Chopping Element

IP.com Disclosure Number: IPCOM000095052D
Original Publication Date: 1965-Aug-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Holloway, JF: AUTHOR

Abstract

This circuit utilizes the bidirectional characteristics of a transistor for switching purposes. The chopper circuit comprises a pair of transistors T1 and T2 connected in parallel across input and output terminals 3 and 4. T1 and T2 are connected in the forward and reverse directions or operational modes, respectively, and are commonly connected at their respective bases. An AC chopper drive signal. which can, for example, be of square or sinusoidal waveform. is applied to the transformer 5 primary. The signal appearing across the transformer 5 secondary is coupled by diode D6 to the common junction of T1 and T2. The peak amplitude of the chopper drive signal is maintained greater than the maximum input voltage applied to terminal 3.

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Parallel Transistor Chopping Element

This circuit utilizes the bidirectional characteristics of a transistor for switching purposes. The chopper circuit comprises a pair of transistors T1 and T2 connected in parallel across input and output terminals 3 and 4. T1 and T2 are connected in the forward and reverse directions or operational modes, respectively, and are commonly connected at their respective bases. An AC chopper drive signal. which can, for example, be of square or sinusoidal waveform. is applied to the transformer 5 primary. The signal appearing across the transformer 5 secondary is coupled by diode D6 to the common junction of T1 and T2. The peak amplitude of the chopper drive signal is maintained greater than the maximum input voltage applied to terminal 3. Thus, the input voltage is prevented from overriding the chopper drive signal and turning on T1 and T2 when the chopper drive signal is in the, negative half-cycle.

During the negative half-cycle, D6 is reverse biased and thus blocks any base current to T1 and T2. As a result, T1 and T2 are turned off during the negative half-cycle. During this period when the transistor pair is in the off condition, in most cases it is preferred that the value of the leakage current from terminal 3 to terminal 4 be zero or negligible. However, in some cases it may be desirable to have some leakage current so as to provide a discrete bias level for the output voltage during the period when the transistor pair is i...