Browse Prior Art Database

Integrated High Speed, Read Only Memory with Slow Electronic Write

IP.com Disclosure Number: IPCOM000095056D
Original Publication Date: 1965-Aug-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Faber, AS: AUTHOR

Abstract

This NDRO memory cell does not require a clear-to-zero operation prior to a write operation. The cell comprises a conventional direct coupled flip-flop arrangement including insulated- gate n-channel field effect transistors T1 and T2. A read gate includes insulated-gate n-channel field effect transistor T3. A write gate includes insulated gate n-channel field effect transistor T4. The source-drain circuit of T3 is connected between word drive line W and sense line S. The gate electrode of T3 is connected to point A defined at the junction of the gate electrode of T1 and the drain electrode of T2. The source-drain circuit of T4 is connected between point A and bit drive line B. The gate electrode of T4 is connected to auxiliary word line AW.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 57% of the total text.

Page 1 of 2

Integrated High Speed, Read Only Memory with Slow Electronic Write

This NDRO memory cell does not require a clear-to-zero operation prior to a write operation. The cell comprises a conventional direct coupled flip-flop arrangement including insulated- gate n-channel field effect transistors T1 and T2. A read gate includes insulated-gate n-channel field effect transistor T3. A write gate includes insulated gate n-channel field effect transistor T4. The source-drain circuit of T3 is connected between word drive line W and sense line
S. The gate electrode of T3 is connected to point A defined at the junction of the gate electrode of T1 and the drain electrode of T2. The source-drain circuit of T4 is connected between point A and bit drive line B. The gate electrode of T4 is connected to auxiliary word line AW.

The operation of T3 and T4 can be understood by considering such elements as variable resistors. Their resistive values are changed from hundreds of ohms to megohms as controlled by the voltage applied at the respective gate electrodes. There is virtually no delay in signal transmission through T3 and T4 when enabled. The only speed limitation is noise coupled via the source-to-drain capacitance.

To effect a write operation, line AW is energized to enable T4. Information to be stored in flip-flop T1-T2 is determined by whether the signal voltage level on bit drive line B is greater or less than the voltage at point A. When the voltage along line B is less than...