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Burst Error Correction in a Binary Erasure Channel

IP.com Disclosure Number: IPCOM000095080D
Original Publication Date: 1965-Sep-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Wolff, CH: AUTHOR

Abstract

This apparatus detects and corrects a burst of errors occurring in a serial data channel. The technique of error encoding is described in ''Error Correcting Codes'', by W. W. Peterson, MIT Press and Wiley & Sons, 1961. During encoding, serial data is written by write circuitry not shown. Following the data, a check character of b bits is written by utilizing the pattern existing in an encoding shift register similar to shift register 28.

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Burst Error Correction in a Binary Erasure Channel

This apparatus detects and corrects a burst of errors occurring in a serial data channel. The technique of error encoding is described in ''Error Correcting Codes'', by W. W. Peterson, MIT Press and Wiley & Sons, 1961. During encoding, serial data is written by write circuitry not shown. Following the data, a check character of b bits is written by utilizing the pattern existing in an encoding shift register similar to shift register 28.

In this serial data channel in which phase encoding is utilized to record digital data, erasures can occur. An erasure is an indication that the circuitry cannot determine whether the binary digit read is a 0 or a 1. Erasure detector 10 emits an output 12 when an erasure is detected. Data detector 14 is utilized to detect 0 and 1 binary digits. The output 16 of detector 14 is shifted into shift register 18. Whenever eight bits of information are accumulated, the eight bits, a byte, are transferred in parallel to central processing unit CPU 20. Bits shifted into register 18 are also counted by bit counter 22 which counts to eight and on every eighth bit emits a pulse which steps byte counter shifted into register 18 are also counted by bit counter 22 which counts to eight and on every eighth bit emits a pulse which steps byte counter 24. The output of detector 14 is also fed to end- around shift register encoder 28 which sums the serial bits to provide an error check.

When an erasure occurs, an output is generated from detector 10 which inhibits And 33 and stops counter 22. Register 18, however, is allowed to shift the erroneous data bits. The erroneous byte or bytes are transferred to CPU 20 in parallel. The data bits also continue to be shifted into encoder 28 to continue to accumulate the check character. When synchronizatio...