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Shared Write Deskewing and Write Circuits

IP.com Disclosure Number: IPCOM000095084D
Original Publication Date: 1965-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 43K

Publishing Venue

IBM

Related People

MacDougall, JP: AUTHOR

Abstract

The circuitry for one tape track X in a parallel track deskewing arrangement for writing NRZI encoded data on magnetic tape. Except for Grey code counter 18, the circuit is duplicated for each of the other tracks recorded in parallel for each byte.

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Shared Write Deskewing and Write Circuits

The circuitry for one tape track X in a parallel track deskewing arrangement for writing NRZI encoded data on magnetic tape. Except for Grey code counter 18, the circuit is duplicated for each of the other tracks recorded in parallel for each byte.

The circuit controls the writing in any selected one of N tape units. Any one tape unit is selected by activation of one of leads 31...38. Each of the write-head windings 15A... 15N writes track X in a different tape unit. Similar circuitry, not shown, is likewise selected by the same lead of 31...38 to operate the write heads for the other tracks in the same tape unit. For example, the head winding 15B and its associated heads in other tracks can be selected by lead 32 to write information in track X and the other tracks of tape unit 2.

Each track X head for a different tape unit is driven by a respective one of head drivers 10A... 10N. Likewise, all of the other write heads have drivers, not shown, in each of the tape units similar to any write driver 10. When one of the N number of tape units is selected by energizing one of lines 31...38 in response to a select command from a computer, And's 11 and 16 for track X of that tape unit are conditioned. Likewise, a similar pair of And's is selected for each of the other tracks in the selected tape unit.

Binary trigger 12 encodes in NRZI form the write signal for track X in the selected tape unit. Similarly, another binary trigger, not shown, is provided for each of the other tracks on a tape. Trigger 12 receives an input pulse from And 13 whenever a 1 bit is to be written in the X bit position of a byte. And 13 is enabled by a 1 bit received on a data input 22. And 13 also receives deskewed write timing pulses from Or 14. Write timing pulses from Or 14 are derived from the selected one of And's 16A... 16N, which provides deskewed write pulses for the X bit position in any selected one of the N tape drives. A similar set of And's 16 and Or 14 are provided for each of the other tracks on a...