Browse Prior Art Database

General Microprogram for VFL Byte Handling

IP.com Disclosure Number: IPCOM000095101D
Original Publication Date: 1965-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 4 page(s) / 68K

Publishing Venue

IBM

Related People

Schnabel, DL: AUTHOR [+2]

Abstract

In the article entitled ``Microprogrammed Byte Moves With Word Offset'' on page 549 of this number, a small complement of auxiliary counting controls augments the control functions of a read-only control store. These auxiliary controls provide effects which can be produced by stored micro-instructions. The number and size of the stored microinstructions, however, are disproportionately greater. This article is concerned with an extension and generalization of a microprogramming technique mentioned in the referenced article.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 40% of the total text.

Page 1 of 4

General Microprogram for VFL Byte Handling

In the article entitled ``Microprogrammed Byte Moves With Word Offset'' on page 549 of this number, a small complement of auxiliary counting controls augments the control functions of a read-only control store. These auxiliary controls provide effects which can be produced by stored micro-instructions. The number and size of the stored microinstructions, however, are disproportionately greater. This article is concerned with an extension and generalization of a microprogramming technique mentioned in the referenced article.

In drawing A, there is an arrangement of microprogrammed sequence controls associated with read-only store RS. These control movement of bytes of information through byte mover subsystem MV of a word handling system. This arrangement is quite similar to the sequence control and mover arrangement shown in the drawing of the referenced article, save for the addition of source and destination field length counters, SC and DC, respectively, as auxiliary controls. Outputs of SC and DC, together with outputs of byte position counters BC and BC' and segments of current micro-instruction outputs supplied by RS to output buffer register DR, control the sequence selection logic SS. This determines the succeeding contents of the microinstruction address register AR. The control system operates in response to micro-instruction control words cyclically withdrawn from RS and delivered to DR. Each withdrawal from RS is specified by the contents of AR. Next address entries to AR are cyclically determined by SS from a combination of conditions. These are selected from a pool of information including the outputs of DR, conditions represented by status triggers ST, main or macroprogram instruction operation codes OP, conditions represented by byte position counters BC and BC', and, in this arrangement, yet to be processed field length conditions, represented by SC and DC.

MV performs And, Or, or Exclusive-Or operations on eight-bit byte subdivisions of thirty-two bit words. The inputs to MV are contained in byte subregisters L0... L3 and M0... M3 of respective word registers L and M. Outputs of MV are returned to a byte subregister of M. L receives information in parallel word units through input word gate LG. M unloads parallel word units via output word gate MC. Within MV, however, information is handled only in byte units. BG0... BG3, U, G0... G3, BG'0... BG'3, V, and W are byte gates associated with MV. Such gates are individually conditioned by control outputs of gate selection logic GS, except that BG0... BG3 and BG'0... BG'3 are jointly controlled. Thus, for example, byte group BG0 and BG'0 is always selected simultaneously.

RS addresses are specified in twelve-bit units. Each twelve-bit address includes at least six bits which are predetermined by the contents of the previous micro-instruction in DR. The remaining six bits are determined by one of three branch methods. In the fir...