Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Microprogrammed Byte Moves with Word Offset

IP.com Disclosure Number: IPCOM000095102D
Original Publication Date: 1965-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 4 page(s) / 59K

Publishing Venue

IBM

Related People

Schnabel, DL: AUTHOR

Abstract

In a system processing intelligence in word units, a subsystem is provided for translating individual byte, or character, subunits of word s while variably offsetting bytes relative to fixed word boundaries. To introduce such offsets within a microprogrammed system having a control store, subsystem controls use byte offset counters. These augment the control functions of the micro-instructions held in the control store. Such arrangements eliminate both a significant number of otherwise necessary micro-instructions from the control store and a significant number of micro-operation control bits from remaining micro-instructions.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 45% of the total text.

Page 1 of 4

Microprogrammed Byte Moves with Word Offset

In a system processing intelligence in word units, a subsystem is provided for translating individual byte, or character, subunits of word s while variably offsetting bytes relative to fixed word boundaries. To introduce such offsets within a microprogrammed system having a control store, subsystem controls use byte offset counters. These augment the control functions of the micro-instructions held in the control store. Such arrangements eliminate both a significant number of otherwise necessary micro-instructions from the control store and a significant number of micro-operation control bits from remaining micro-instructions.

The control store consists of a read-only, microprogram store RS, its associated address selection AR and output buffer DR registers. Control micro- instructions, cyclically selected in accordance with current contents of AR, are deposited in DR. Successive entries to AR are determined by sequence selecting logic circuitry SS. The latter is ordinarily conditioned by a portion of the output of DR taken in combination with variable condition signals. These are determined either as a function of the values of a selected group of status triggers ST or as a function of a selected group of main program instruction operation code bits OP. Gate selection logic GS is used to translate outputs of DR into gate control signals. Such are distributed to all gates throughout an information handling system associated with RS.

This system handles information serially-by-word and parallel-by-bits of a word. A word comprises a group of thirty-two bits. However, a subsystem of this system, associated with mover circuit MV, handles byte units of information, each containing eight bits, serial-by-byte and parallel-by-bits of a byte.

This subsystem comprises word registers L and M, MV, and byte position counters BC and BC' respectively associated with L and M. BC and BC' are specific examples of byte offset counters. These are associated with the subsystem to avoid the relatively less effective expansion of RS, required to produce equivalent effects. Since each counter must be able to count four byte positions within a word, each is provided with two binary counting stages.

L and M are each subdivided into four byte subregisters L0... L3 and M0... M3. Associated with L are word input gate LG, four byte output gates BG0... BG3, the latter individually associated with L0... L3, and a byte transmission gate U common to all of BG0... BG3. M is associated with byte input gates G0... G3, individually feeding into M0... M3, a word output gate MG, byte output gates BG'0... BG'3 extending from respective byte outlets of M0... M3, and a byte transmission gate V common to all of the groups of input gates G0... G3. U and V extend to respective left and right byte inputs of MV.

MV can perform logical operations, such as And, Or and Exclusive-Or, on one of two byte inputs funneled selectively through...