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Executing Programs while they are being Loaded

IP.com Disclosure Number: IPCOM000095112D
Original Publication Date: 1965-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Maling, K: AUTHOR

Abstract

Most large computers have a hierarchy of storage devices with most programs being kept in low-speed store until it is desired to execute them. Therefore, when it is desired to execute a program, transfer of the information from a low-speed to a high-speed store must first be effected. If the high-speed store is large enough, some other program residing in this store can be executed while the transfer is being effected. However, it is not always either possible or desirable to do this. In this method, a program is executed while it is being transferred from a low-speed store into a high-speed store.

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Executing Programs while they are being Loaded

Most large computers have a hierarchy of storage devices with most programs being kept in low-speed store until it is desired to execute them. Therefore, when it is desired to execute a program, transfer of the information from a low-speed to a high-speed store must first be effected. If the high-speed store is large enough, some other program residing in this store can be executed while the transfer is being effected. However, it is not always either possible or desirable to do this. In this method, a program is executed while it is being transferred from a low-speed store into a high-speed store.

In operation, four registers for each level of low-speed store in the hierarchy are required. These are: 1. Transfer from register TF which stores the address in low-speed store from which the last word was taken. 2. Transfer to register TT which stores the last address in high-speed memory to which a word was transferred. 3. Local Instruction Counter LIC which stores the address of the last instruction in high-speed memory which was executed. 4. Word Counter WC which stores the initial length of the program being transferred and is decremented each time a word is transferred.

A special branch instruction sets the system to a mode in which LIC is never allowed to run ahead of the address in TT. However, if the address in LIC is greater than or equal to the address in TT, an interrupt occurs in the form of, for example, the...