Browse Prior Art Database

Array Charging Technique

IP.com Disclosure Number: IPCOM000095122D
Original Publication Date: 1965-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Lake, JA: AUTHOR

Abstract

High-impedance resistors maintain the stray capacitance of a memory array at a charged value and thus speed the rise times of core drive currents.

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Array Charging Technique

High-impedance resistors maintain the stray capacitance of a memory array at a charged value and thus speed the rise times of core drive currents.

The conductors making up a memory array drive system form a large stray capacitance. This must be charged to the power supply voltage prior to establishment of current now through a selected magnetic core drive winding. In this X or Y drive system, resistors R1 and R2 perform this charging function. R1 and R2 are of relatively high resistance values and have no significant effect on the circuit during actual memory drive pulses. These bypass R1 and R2 through transistor switches 3 and 4. R1 and R2 provide a connection to the power supply to maintain the array capacitance charged by recharging it between cycles.

The drive system includes a large number of core winding wires 5 which are diode-connected through transistor switches 3... 7 in a manner which permits current flow in either direction on a selected wire. Selection of switch 3 and switch 7a causes current flow on conductor 5a from left to right, read half- selecting the related cores 8. There is no delay required to charge the array capacitance which is already charged through R1 and R2.

In operation, all switches are normally open. As operation begins, the switches have been open long enough for the array capacitance to have been charged to a potential of +V volts. When switch 3 is closed, no current flows, for both terminals of the swi...