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Single Arithmetic Unit Vector Processor

IP.com Disclosure Number: IPCOM000095130D
Original Publication Date: 1965-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 33K

Publishing Venue

IBM

Related People

Senzig, DN: AUTHOR

Abstract

The system performs multiple arithmetic operations N under control of a single instruction counter. However, the system utilizes M very high-speed arithmetic units instead of the N arithmetic units M < < N as in Solomon. Further, unlike Solomon, the memory organization is such that there is no fixed amount of memory which is assigned to a given processor. The organization presented here permits unrestricted access to a single memory. For example, an add instruction results in N, typically, N = 16, pairs of operands being fetched from memory, passed to the arithmetic units and sequentially added, so that sixteen sums appear in sixteen accumulators.

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Single Arithmetic Unit Vector Processor

The system performs multiple arithmetic operations N under control of a single instruction counter. However, the system utilizes M very high-speed arithmetic units instead of the N arithmetic units M < < N as in Solomon. Further, unlike Solomon, the memory organization is such that there is no fixed amount of memory which is assigned to a given processor. The organization presented here permits unrestricted access to a single memory. For example, an add instruction results in N, typically, N = 16, pairs of operands being fetched from memory, passed to the arithmetic units and sequentially added, so that sixteen sums appear in sixteen accumulators.

The arithmetic capability of the system is concentrated in a smaller number of very powerful arithmetic units. The system controls stream arithmetic operands to and from these units.

The high-speed arithmetic units are assumed to complete a single multiply, floating add, or divide in a very few, typically, one or two, minor cycles. A multiplier that meets these requirements is described by Wallace/2/. A floating point add unit is conventional. A modification of the divide unit of the Harvard Mark IV meets the requirements. The latter operation is discussed by Richards for a decimal divider and extension to radix two is not difficult.

The system also utilizes two high-speed register arrays X and Z each having N word storage locations for storing operands accessed from memory and results from the arithmetic unit. Since a single arithmetic operation is very fast, it is possible to include register to register and memory to selected register operations of the usual single operation computers. Thus, the machine can be operated in a vector arithmetic mode, N operands per instruction. Unlike Solomon, the registers can be used as temporary storage accumulators as in some data processing...