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Field Effect Transistor Clocked Logic

IP.com Disclosure Number: IPCOM000095148D
Original Publication Date: 1965-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Ruoff, CE: AUTHOR

Abstract

The family of circuits offers properties that are very advantageous in the large scale integration of computer circuits. They are constructed entirely of a single type of insulated gate, enhancement mode, N or P channel field effect transistors. All of the transistors are the same size with the same gain but have very loose tolerances on their parameters.

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Field Effect Transistor Clocked Logic

The family of circuits offers properties that are very advantageous in the large scale integration of computer circuits. They are constructed entirely of a single type of insulated gate, enhancement mode, N or P channel field effect transistors. All of the transistors are the same size with the same gain but have very loose tolerances on their parameters.

The systems require clock logic. An illustrative set of four phase delayed timing pulses is shown in drawing 1. Each logic block which is driven by a phi(A) and phi(B) must be preceded and followed by a logic block which is driven by a phi(C) and phi(D). Conversely, blocks driven by phi(C) and phi(D) must be preceded and followed by blocks driven by phi(A) and phi(B). This is necessary to allow stepping of logical information through a series of such circuits. This is because interrogation must be preceded by a setting of the storage node to a known value.

For operation of the above circuits refer, for example, to drawing 2. The output node of the logic circuit is reset to -10 volts by clock pulse phi(A) applied to transistor 10. After resetting, logical inputs are applied to input points R, S, T, U or V of the field effect transistors 14. Subsequent to this the condition of the logic is interrogated by pulse phi(B) applied to transistor 12. If a pulse is applied to any of the field effect transistors 14, the output node is at zero or ground potential. Drawing 2 represents a...