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Junction Isolation for Isolating Integrated Devices Formed by an Etch and Regrowth Technique

IP.com Disclosure Number: IPCOM000095166D
Original Publication Date: 1965-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Doo, VY: AUTHOR

Abstract

Starting with a P-type monocrystalline silicon wafer, a silicon dioxide layer or film is grown or formed on the surface as in A. Portions of the oxide layer are etched away by photolithographic masking and etching techniques. This leaves an oxide layer network on the surface of the wafer as in B. The exposed portions of the silicon wafer are etched away using the oxide network layer as a mask. About 4-6 microns of silicon are etched away using either an aqueous acid solution or a vapor etch as In C.

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Junction Isolation for Isolating Integrated Devices Formed by an Etch and Regrowth Technique

Starting with a P-type monocrystalline silicon wafer, a silicon dioxide layer or film is grown or formed on the surface as in A. Portions of the oxide layer are etched away by photolithographic masking and etching techniques. This leaves an oxide layer network on the surface of the wafer as in B. The exposed portions of the silicon wafer are etched away using the oxide network layer as a mask. About 4-6 microns of silicon are etched away using either an aqueous acid solution or a vapor etch as In C.

N+ and then N-type monocrystalline silicon layers are epitaxially grown on the unmasked monocrystalline silicon surface. There is use of the silicon dioxide network layer as a mask for the silicon etching operation and the regrowth of monocrystalline silicon. Subsequently by diffusion techniques, P-type base regions are formed in the N-type epitaxially grown collector regions. Then N-type emitter regions are formed in the P-type base regions to provide transistor structures as in D.

These can be electrically connected up in a desired circuit arrangement. Such is effected by providing electrical contacts to the active portions of each transistor device and properly interconnecting the devices. By applying a reverse bias potential between the N-type collector regions and the P-type substrate, junction isolation is achieved for each of the formed transistor devices.

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