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Isolation Method and Structure for Integrated Devices

IP.com Disclosure Number: IPCOM000095167D
Original Publication Date: 1965-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Pieczonka, WA: AUTHOR [+2]

Abstract

This method electrically isolates each of a plurality of semiconductor devices formed in a single substrate.

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Isolation Method and Structure for Integrated Devices

This method electrically isolates each of a plurality of semiconductor devices formed in a single substrate.

Each semiconductor device is made either by epitaxially growing layers of the desired conductivity type on a monocrystalline semiconductor wafer or by diffusion of impurities into the appropriate semiconductor regions of a semiconductor wafer. Subsequently, a network of isolation moats is formed, such as by etching, about each semiconductor device. After formation of the isolation moats, the surface of the wafer is coated with a dielectric material. This fills in the moat and covers the top surface of the wafer. In one example, the dielectric material used is a glass that has a coefficient of expansion that closely matches the coefficient of expansion of the semiconductor material. For example, where silicon is used as the semiconductor material, a borosilicate type glass such as PYREX* has a coefficient of expansion that closely matches the coefficient of expansion of silicon.

Holes can be etched in the surface glass layer to reach the different active portions of each semiconductor device in order to permit the subsequent formation of ohmic contacts to each device. This arrangement uses dielectric isolation between the sides of adjacent semiconductor devices. In addition, it uses junction isolation by applying a reverse bias between the N-type collector of each semiconductor device and the substrate o...