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Two Phase Latched Shifter

IP.com Disclosure Number: IPCOM000095217D
Original Publication Date: 1965-Oct-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Earle, J: AUTHOR

Abstract

This circuit enables data either from a number of different sources or from different orders of a register to be set into a latch circuit. The data is available at both a true and complement output terminal after passing through only one logical level.

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Two Phase Latched Shifter

This circuit enables data either from a number of different sources or from different orders of a register to be set into a latch circuit. The data is available at both a true and complement output terminal after passing through only one logical level.

The latched shifter is constructed of one type of circuitry. This is a current switching Or which generates both true, lower right, and complemental, upper right, outputs. Normally, each output at the collector of a current switching transistor drives an emitter-follower transistor. There are four data input lines
1...4. On each input, a more negative input signal indicates the presence of data. Lines 1...4 associated with them gate lines 5... 8, respectively. All gates have the same timing but are selectively energized to enter the data on the associated data line.

A pair of data and gate lines, e.g., 1 and 5, are inputs to an Or, e.g., 9. A gate line is an input to an Inverter, e.g., 13. An Inverter is the same logic block but uses only one input and drives only the complemental output line before the emitter-follower, e.g., 17. For an associated pair, e.g., Or 9 and I13, the collector of the transistor on the true output of Or 9 and that of the complemental output transistor on the 113 have a common load resistor. This results in a Dot-And logical combination of the two outputs.

This output signal passes through the emitter-follower, e.g., EF17, for the true output of the Or. The complemental output of an Or, e.g., Or 9, also passes through an emitter-follower, e.g., EF21. The corresponding emitter-followers of the two groups of four EF' s have common emitter load resistors and thus provide a Dot-Or function of the output signals. The outputs of EF's 21...24 on line 25 are true data signals and those of EF's 17...20 on line 26 are the complemental data signals.

During the time the selected gate signals on lines 5...8 are positive, i.e., not gate, the complemental outputs of Or's 9...12 are all negative. Thus, line 25 is negative. Also during this time, the outputs of 1's 13...16 are all negative. Consequently, even though the true outputs of Or's 9...12 are positive, the And func...