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Binary Exclusive Or Carry

IP.com Disclosure Number: IPCOM000095218D
Original Publication Date: 1965-Oct-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 31K

Publishing Venue

IBM

Related People

Tan, KG: AUTHOR

Abstract

In very high-speed computers, it is essential to keep data paths to a minimum length in terms of the number of logic levels through which a signal must pass. One of the longer data paths is through the adder. In some technologies, this path can be shortened.

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Binary Exclusive Or Carry

In very high-speed computers, it is essential to keep data paths to a minimum length in terms of the number of logic levels through which a signal must pass. One of the longer data paths is through the adder. In some technologies, this path can be shortened.

In carry lookahead adders, it has been usual to logically separate the adder into small units of a few denominational orders. The units are then combined into groups. The groups are combined into a number of sections. For any denomination, a carry-in signal can be developed by entries in lower denominations of the unit to which the denominational order belongs. Alternatively, a carry-in can be developed by a carry generated by a lower value unit of the group and propagated through intervening units of the group into the denomination. A carry-in signal can arise from a carry signal generated by a lower value section and propagated through the intervening lower value sections and groups. All such possible carry-in signals have usually been Ored together. The resultant signal is then combined in an Exclusive-Or with the modulo-2 sum of the two input signals of the denomination. In general, the unit carry signal for a denomination is generated at about the same time as the modulo-2 sum. The group carry signal appears after passing through at least another logic level. The section carry signal appears after at least still another logic level and the required Or and Exclusive-Or account for two more logic levels.

One level of logic and its related timing can be saved by the rearrangement in the drawing. The modulo-2 half sum is generated in Exclusive-Or (V) 1. The unit carry signal into that denomination is generated on Dot-Or output line 2 by one of a group of And's (A) 3, 4, etc. These receive the carry generate and carry propagate signals from the lower denominations of the unit. The signals from V 1 and on line 2 are com...